This invention relates to an electrically rewritable nonvolatile semiconductor memory device and more particularly to a nonvolatile semiconductor memory device for raising a bit line potential of floating writing type by use of a coupling capacitor between bit lines to a level equal to or higher than a power supply voltage and using the same.
Recently, as one of electrically erasable and programmable read only memory devices (EEPROMs), a NAND type EEPROM is proposed. The EEPROM has a plurality of memory cells each having an n-channel MOSFET structure in which, for example, a floating gate used as a charge storage layer and a control gate are stacked and a preset number of memory cells are serially connected with the sources and drains commonly used by the adjacent memory cells and are connected to the bit line as one unit. One end of the series-connected memory cells is connected to the bit line via a selection transistor and the other end thereof is connected to a source line via another selection transistor.
The data programming, data erasing and data readout operations in the NAND type EEPROM are effected as follows.
First, the data programming process is effected for the series-connected memory cells starting from the memory cell which lies farthest apart from the bit line. A voltage of 0 V ("0" programming) or an external power supply voltage Vcc ("1" programming) is applied to the bit line according to the programming data. If an internal power supply voltage Vdd is created by lowering the external power supply voltage Vcc in the chip and used, 0 V ("0" programming) or the internal power supply voltage Vdd ("1" programming) is applied to the bit line. In this case, the external power supply voltage Vcc (or the internal power supply voltage Vdd) applied to the bit line is generally called a programming non-selection voltage.
The gate voltage of the selection transistor connected to the bit line is set at "Vcc" (or "Vdd") and the gate voltage of the selection transistor connected to the source line is set at "0 V". At this time, in the "0" programming process, the selection transistor connected to the bit line is turned ON and "0 V" is transmitted to the channel of the cell into which "0" is programmed. Further, in the "1" programming process, the selection transistor connected to the bit line is turned OFF and the voltage of the channel of the cell into which "1" is programmed becomes "Vcc-Vthsg" (or Vdd-Vthsg:Vthsg is the threshold voltage of the selection transistor) and the channel is set into the electrically floating state.
After this, a raised programming voltage Vpgm (=approx. 20 V) is applied to the control gate of the cell selected for programming and an intermediate voltage Vpass (=approx. 10 V) is applied to the control gates of other programming non-selected cells and the gates of the selection transistors. As a result, if programming data is "0", the channel voltage is 0 V, and therefore, a high voltage is applied between the floating gate and the p-type well region of the selected cell so as to cause electrons to be injected from the p-type well region into the floating gate by the tunnel effect. on the other hand, if programming data is "1", the voltage of the channel in the floating state is raised to approx. 6 V by the capacitive coupling with the control gate, and no electrons are injected and the threshold voltage is not shifted.
The data erasing operation is simultaneously effected for each block unit. That is, the voltages of the control gates of all of the cells of the block in which data is erased and the gates of the selection transistors are set to "0 V " and a raised erase voltage VEE (=approx. 20 V) is applied to the p-type well region and n-type substrate. As a result, in the cells of the block in which data is erased, electrons in the floating gates are discharged into the p-type well region and the threshold voltages are shifted in the negative direction.
The data readout operation is effected by precharging the bit line and then setting the bit line in the electrically floating state, setting the voltage of the control gate of the cell selected for readout to "0 V", setting the voltages of the control gates of the other cells and the voltages of the gates of the selection transistors to the external power supply voltage Vcc (or the internal power supply voltage Vdd; "Vcc" and "Vdd" are both set at approx. 3 V), setting the voltage of the source line to 0 V, and determining whether or not a current flows in the channel of the cell selected for readout by use of the bit line. That is, since the cell is set in the "OFF" state if data programmed in the cell is "0" (the threshold voltage Vth of the cell&gt;0), the voltage of the bit line is kept at the precharge voltage. In contrast, since the cell is set in the "ON" state if data programmed in the cell is "1" (the threshold voltage Vth of the cell&lt;0), the voltage of the bit line is lowered from the precharge voltage by .DELTA.V. By sensing and amplifying such a voltage variation of the bit line by use of the sense amplifier, data of "0" or "1" is read out from the cell.
In the conventional data programming method described above, the voltage of the channel is set to an intermediate voltage of approx. 6 V by the capacitive coupling between the control gate and the channel at the "1" programming time. However, if the capacitance associated with the diffused layer of the cell is larger than the capacitance between the control gate and the channel, the voltage of the channel will be raised by approx. 3 V even if the voltage of the control gate is set to 10 V. As a result, the voltage difference between the control gate and the channel is small and "erroneous programming" may occur in the cell in which "1" is to be programmed.
In order to suppress the possibility that "erroneous programming" may occur in the cell in which "1" is to be programmed, it is considered that the programming non-selection voltage applied to the bit line at the "1" programming time is set to be higher than the external power supply voltage Vcc or internal power supply voltage Vdd.
However, in this case, it is necessary to additionally provide a high voltage generating circuit for generating a voltage higher than Vcc or Vdd. If such a high voltage generating circuit is mounted on the chip, the chip area is greatly increased. Further, if the programming non-selection voltage higher than the voltage Vcc or Vdd is applied from the high voltage generating circuit to the bit line at the "1" programming time, time for charging the bit line takes a long time since the capacitance associated with the bit line is large, and as a result, the data programming speed becomes low.
Particularly, the capacitance associated with the bit line in the NAND type EEPROM is relatively larger than that in the other semiconductor memories. The reason is as follows.
In the NAND type EEPROM, great importance is attached to how small the chip is and how large the integrated memory capacity is. For this reason, unlike the DRAM in which great importance is attached to the high-speed operation, for example, the memory cell array is not finely divided and the number of divisions of the memory cell array is set as small as possible. This is because the number of peripheral circuits such as row decoders and sense amplifiers is suppressed to minimum.
Therefore, if the high voltage generating circuit for setting the programming non-selection voltage higher than the voltage Vcc or Vdd at the "1" programming time is provided for the NAND type EEPROM, time for charging the bit line takes a long time and the current consumption becomes extremely large.
Further, if the EEPROM is operated by the internal power supply voltage Vdd, for example, a large current flows when 4000 bit lines are charged at the programming time and there occurs a possibility that the internal power supply voltage Vdd will be lowered. That is, in order to further enhance the breakdown voltage of the internal transistors as the semiconductor memory is more miniaturized, the internal power supply voltage Vdd is obtained by lowering the external power supply voltage Vcc by use of a voltage lowering circuit. Since the voltage lowering circuit also functions as a resistor element between the external power supply voltage Vcc and the internal power supply voltage Vdd, a lowering in the internal power supply voltage Vdd when the bit line is precharged increases in comparison with a case wherein the voltage lowering circuit is not used and Vcc=Vdd.
In order to cancel the lowering in the internal power supply voltage Vdd at the time of precharging of the bit lines, the number of divisions of the memory cell array is increased to reduce the length of each bit line, but in this case, the numbers of row decoders and sense amplifiers are increased and the chip area becomes large.